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ISL9021
Datasheet June 12, 2009 FN6867.1
250mA Single LDO with Low IQ, Low Noise and High PSRR LDO
The ISL9021 is a single LDO providing high performance low input voltage, high PSRR. It delivers guaranteed continuous 250mA load current and is stable with 1F to 4.7F of output capacitance (30%) with an ESR range of 5m to 400m. The input voltage range for the ISL9021 is between 1.5V to 5.5V and the output voltage comes in many fixed voltage options with 1.8% accuracy over temperature, line and load ranges. Other output voltage within the range of 0.9V to 3.3V may be available upon request. The ISL9021 has typical PSRR of 75dB @ 10kHz and 50dB @ 1MHz. The reverse current protection feature prevents current from flowing back to the power source when the output voltage is pulled higher than the input. The ISL9021 is offered in tiny 4-bump 1.155mmx0.975mm WLCSP and 1.6mmx1.6mm 6 Ld TDFN packages.
Features
* High Performance LDO with 250mA guaranteed continuous output current * Input Voltage Range: 1.5V to 5.5V * Output Voltage Range: 0.9V to 3.3V * High PSRR: 75dB @ 10kHz, 50dB @ 1MHz * Low Quiescent Current: 35A * Dropout Voltage: <150mV @ 250mA * Stable with 1F to 4.7F Output Capacitance (30%) with an ESR range of 5m to 400m * 1.8% Output Accuracy Over-Temperature/Load/Line * Soft-start Limits Input Current Surge During Enable * Current Limit and Overheat Protection * -40C to +85C Operating Temperature Range * Available in 1.155mmx0.975mm 4-bump WLCSP Package and 1.6mmx1.6mm 6 Ld TDFN * Pb-free (RoHS compliant)
Pinouts
ISL9021 (6 LD 1.6x1.6 TDFN) TOP VIEW
Applications
* PDAs, Cell Phones and Smart Phones * Portable Instruments, MP3 Players * Handheld Devices including Medical Handhelds
VIN 1 NC 2 EN 3
6 5
VO NC
4 GND
ISL9021 (4 BALL 1.155x0.975 WLCSP) TOP VIEW
GND EN A2 A1 B2 B1 VOUT VIN
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL9021 Ordering Information
PART NUMBER ISL9021II1Z-T (Notes 1, 3) ISL9021II2Z-T (Notes 1, 3) ISL9021II3Z-T (Notes 1, 3) ISL9021II4Z-T (Notes 1, 3) ISL9021IIBZ-T (Notes 1, 3) ISL9021IICZ-T (Notes 1, 3) ISL9021IIFZ-T (Notes 1, 3) ISL9021IIGZ-T (Notes 1, 3) ISL9021IIJZ-T (Notes 1, 3) ISL9021IIKZ-T (Notes 1, 3) ISL9021IIMZ-T (Notes 1, 3) ISL9021IINZ-T (Notes 1, 3) ISL9021IIPZ-T (Notes 1, 3) ISL9021IIRZ-T (Notes 1, 3) ISL9021IISZ-T (Notes 1, 3) ISL9021IITZ-T (Notes 1, 3) ISL9021IIWZ-T (Notes 1, 3) ISL9021IIYZ-T (Notes 1, 3) ISL9021IRU1Z-T (Notes 1, 4) ISL9021IRU2Z-T (Notes 1, 4) ISL9021IRU3Z-T (Notes 1, 4) ISL9021IRU4Z-T (Notes 1, 4) ISL9021IRUBZ-T (Notes 1, 4) ISL9021IRUCZ-T (Notes 1, 4) ISL9021IRUFZ-T (Notes 1, 4) ISL9021IRUGZ-T (Notes 1, 4) ISL9021IRUJZ-T (Notes 1, 4) ISL9021IRUKZ-T (Notes 1, 4) ISL9021IRUMZ-T (Notes 1, 4) ISL9021IRUNZ-T (Notes 1, 4) ISL9021IRUPZ-T (Notes 1, 4) ISL9021IRURZ-T (Notes 1, 4) ISL9021IRUSZ-T (Notes 1, 4) ISL9021IRUTZ-T (Notes 1, 4) ISL9021IRUWZ-T (Notes 1, 4) ISL9021IRUYZ-T (Notes 1, 4) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. For other output voltages, contact Intersil Marketing. 3. These Intersil Pb-free WLCSP and BGA packaged products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING 0211 0212 0213 0214 021B 021C 021F 021G 021J 021K 021M 021N 021P 021R 021S 021T 021W 021Y S1 S9 S3 S0 S4 S6 T0 T2 T3 T4 T5 R8 S7 T1 S5 S8 S21 R9 VO Voltage (Note 2) 1.1 2.1 1.3 1.0 1.5 1.8 2.5 2.7 2.8 2.85 3.0 3.3 1.85 2.6 1.6 1.9 1.2 0.9 1.1 2.1 1.3 1.0 1.5 1.8 2.5 2.7 2.8 2.85 3.0 3.3 1.85 2.6 1.6 1.9 1.2 0.9 TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE Tape & Reel (Pb-free) 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 4 Ball WLCSP 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN PACKAGE DWG. # W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 W2x2.4 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6 L6.1.6x1.6
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FN6867.1 June 12, 2009
ISL9021
Absolute Maximum Ratings
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V
Thermal Information
Thermal Resistance (Typical, Note 5) JA (C/W) 4 Ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135.64 6 Lead TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Junction Temperature Range . . . . . . . . . . . . . . . . .-40C to +125C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications
TA = -40C to +85C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 1.5V; CIN = 1F; CO = 1F; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER DC CHARACTERISTICS Supply Voltage VIN Undervoltage Lockout Threshold Ground Current Shutdown Current Output Voltage Accuracy
VIN VUVLO+ VUVLOIDD IDDS VIN Rising VIN Falling Output Enabled; IO = 0; VIN = 1.5V to 5.5V VIN = 5.5V, EN = Low, IO = 0 VIN = VO + 0.5V to 5.5V, IO = 1mA to 150mA, TJ = +25C IMAX ILIM VDO TSD IO = 250mA; VO > 1.8V Continuous
1.5 1.425 1.3 1.375 35 0.1 -0.8
5.5 1.5
V V V
50 1.0 +0.8 +1.8
A A %
VIN = VO + 0.5V to 5.5V, IO = 1mA to 150mA, TJ = -40C to +125C -1.8 Maximum Output Current Internal Current Limit Dropout Voltage (Notes 6, 7) Thermal Shutdown Temperature Thermal Shutdown Hysteresis AC CHARACTERISTICS Ripple Rejection (Note 6) VIN = 4.5V, VO = 3.3V @ 1kHz VIN = 4.5V, VO = 3.3V @ 10kHz VIN = 4.5V, VO = 3.3V @ 1MHz Output Noise Voltage (Note 6) DEVICE START-UP CHARACTERISTICS Device Enable Time LDO Soft-start Ramp Rate EN LOGIC CHARACTERISTICS Input Low Voltage Input High Voltage Input Leakage Current NOTES: 6. Limits established by characterization and are not production tested. 7. Dropout voltage is measured as VIN - VO, when VO is 4% lower than the value of VO; when VIN = VO + 0.5V. VIL VIH IIL, IIH 1.1 tEN tSSR Time from assertion of the EN pin to when the output voltage reaches 95% of the VO (nom) Slope of linear portion of LDO output voltage ramp during start-up 250 30 VIN = 4.2V, TA = +25C, BW = 10Hz to 100kHz, IO = 10mA 60 75 50 8.5*VO 250 260 150 160 20
mA mA 250 mV C C
dB dB dB VRMS 600 60 s s/V
0.4
V V
0.1
A
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FN6867.1 June 12, 2009
ISL9021 Typical Operating Performance
45 QUIESCENT CURRENT (A) QUIESCENT CURRENT (A) 40 35 30 25 20 T = -25C 15 10 5 0 1.5 2.5 3.5 4.5 INPUT VOLTAGE (V) 5.5 T = -40C T = 0C T = ROOM TEMP T = +45C T = +85C 45 40 35 30 25 20 15 10 5 0 1.5 2.5 3.5 4.5 INPUT VOLTAGE (V) 5.5 T = -25C T = -40C T = 0C T = ROOM TEMP T = +45C T = +85C
FIGURE 1. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT = 0.9V)
FIGURE 2. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT = 1.85V)
50 T = ROOM TEMP QUIESCENT CURRENT (A) 40 30
T = +45C
1.95 T = +85C 1.90 +85C 1.85 Vo (V) T = 0C 1.80 -40C 1.75 1.70 1.65 +25C
20 T = -40C 10 0 -10 3.5
T = -25C
4.0
4.5 5.0 INPUT VOLTAGE (V)
5.5
6.0
1.60 0
50
100
150 Io (mA)
200
250
300
FIGURE 3. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT = 3.3V)
FIGURE 4. LOAD REGULATION vs TEMPERATURE (VOUT = 1.85V)
2.00 1.95 1.90 1.85 Vo (V) 1.75 1.70 1.65 1.60 1.55 1.50 2.5 3.5 4.5 VIN(V) 5.5 6.5 +85C -40C Vo (V) 1.80 +25C
3.5 3.4 3.3 3.2 -40C 3.1 3.0 2.9 2.8 0 50 100 150 Io (mA) 200 250 300 +25C +85C
FIGURE 5. LINE REGULATION vs TEMPERATURE (VOUT = 1.85V)
FIGURE 6. LOAD REGULATION vs TEMPERATURE (VOUT = 3.3V)
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FN6867.1 June 12, 2009
ISL9021 Typical Operating Performance (Continued)
3.50 3.45 3.40 3.35 Vo (V) 3.30 3.25 3.20 3.15 3.10 3.05 3.00 3.5 4.0 4.5 VIN (V) 5.0 5.5 6.0 -40C +25C +85C Vo (V) 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0 50 100 150 Io (mA) 200 250 300 -40C +25C +85C
FIGURE 7. LINE REGULATION vs TEMPERATURE (VOUT = 3.3V)
FIGURE 8. LOAD REGULATION vs TEMPERATURE (VOUT = 0.9V)
VIN = 2.7V 1.00 0.95 0.90 Vo (V) 0.85 0.80 0.75 IOUT 0.70 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 6.0 IOUT = 1mA TO 250mA VOUT +85C VOUT = 1.85V +25C COUT = 1F
-40C
FIGURE 9. LINE REGULATION vs TEMPERATURE (VOUT = 0.9V)
FIGURE 10. LOAD TRANSIENT RESPONSE
VOUT = 1.85V VOUT
VIN = 2.7V COUT = 4.7F
IOUT IOUT = 1mA TO 250mA
FIGURE 11. LOAD TRANSIENT RESPONSE
FIGURE 12. ENABLE FUNCTION (VIN = 3.6V, VOUT = 1.85V, COUT 1F)
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FN6867.1 June 12, 2009
ISL9021 Typical Operating Performance (Continued)
-20 -30 -40 PSRR (dB) -50 -60 -70 -80 -90 100 IO = 0A VIN = 4.5VDC + 50mVAC COUT = 1F IO = 10mA
1k
10k FREQUENCY (Hz)
100k
1M
FIGURE 13. POWER SUPPLY REJECTION vs FREQUENCY
Pin Descriptions
PIN NAME VIN GND EN VO E-Pad IC Supply/LDO Input. Connect a 1F capacitor to GND. System ground pin. LDO Enable. When this signal goes high, the LDO is turned on. LDO Output. Connect a 1F to 4.7F capacitor to GND. For TDFN package option only. Connect it to the system ground. DESCRIPTION
Typical Application
ISL9021 VIN (1.5V TO 5.5V) ON ENABLE OFF C1 EN GND VIN VO VOUT
C2
C1, C2: 1F X5R CERAMIC CAPACITOR
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FN6867.1 June 12, 2009
ISL9021 Block Diagram
VIN
PASS ELEMENT
VOUT
EN
TEMP SENSOR
CONTROL LOGIC
SHORT-CIRCUIT PROTECTION THERMAL PROTECTION SOFT-START
VOLTAGE AND REFERENCE GENERATOR
+
BANDGAP
GND
7
FN6867.1 June 12, 2009
ISL9021 Functional Description
The ISL9021 is a high performance low-dropout regulator (LDO) with 250mA sourcing capability. The extra low ground current makes this part a good choice for handheld product applications. The device also incorporates overcurrent, thermal shutdown, reverse current protections, and soft-start features. Thermal shutdown protects the device against overheating. Soft-start limits the start-up input current surges. In some applications, the output voltage may be externally pulled higher than input, or the input voltage could be connected to ground, or connected to some voltage lower than the output side. The ISL9021 features reverse current protection; that can block the reverse current from output to input. The ISL9021's reverse current protection is intended to block reverse conduction if output voltage is higher than input voltage.
Input and Output Capacitors
The ISL9021 provides a linear regulator that has low quiescent current, fast transient response, and overall stable operation across the recommended operating conditions. A ceramic capacitor (X5R or X7R) with a capacitance of 1F to 4.7F with an ESR up to 400m is suitable for the ISL9021 to maintain its output stability. The ground connection of the output capacitor should be routed directly to the GND pin of the device, and also placed close to the IC. Similarly for the input capacitor, usually a 1F ceramic capacitor (X5R or 7R) is suitable for most cases, but if a large, fast rising load transient condition is expected, a higher value input capacitor may be necessary to achieve satisfactory performance.
Enable Control
The ISL9021 has an enable pin. When EN is low, the IC is in shutdown mode. In this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1A(typ). Driving this pin high will turn on the device.
Board Layout Recommendations
A good PCB layout is an important step to achieve good performance. It is recommended to design the board with separate ground planes for input and output, and connect both ground planes at the GND pin of the IC. Consideration should be taken when placing the components and routing the trace to minimize the ground impedance, and keep the parasitic inductance low. Usually the input/output capacitors should be placed as close to the IC as possible with a good ground connection.
LDO Protections
The ISL9021 offers several protection functions, making it ideal for use in battery-powered applications.The ISL9021 provides short-circuit protection by limiting the output current at current limit of 260mA(min). If the short circuit lasts long enough, the die temperature increases, and the over-temperature protection circuit will shut down the output. When the die temperature reaches about +145C, thermal protection starts to work with output being loaded with at least 50mA. Once the die temperature drops to about +110C, the LDO will resume operation beginning with a soft-start.
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FN6867.1 June 12, 2009
ISL9021 Wafer Level Chip Scale Package (WLCSP 0.4mm Ball Pitch)
D
W2x2.4
2x2 ARRAY 4 BALL WAFER LEVEL CHIP SCALE PACKAGE SYMBOL A A1 A2 MILLIMETERS 0.44 Min, 0.495 Nom, 0.55 Max 0.190 0.030 0.305 0.025 0.270 0.030 1.155 0.020 0.400 BASIC 0.975 0.020 0.400 BASIC 0.400 BASIC 0.200 BASIC 0.00 BASIC NUMBER OF BUMPS: 4 Rev. 2 6/08
E
b D
PIN 1 TOP VIEW
D1 E E1 e SD SE
A2 A1 A
NOTES: 1. All dimensions are in millimeters.
b SIDE VIEW
e ( D1 )
2 SE 1 B b A e ( E1 )
SD BOTTOM VIEW
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN6867.1 June 12, 2009
ISL9021
Package Outline Drawing
L6.1.6x1.6
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD COL PLASTIC PACKAGE (UTDFN COL) Rev 1, 11/07
2X 1.00 1.60 6 PIN 1 INDEX AREA A PIN #1 INDEX AREA 6 B 1 4X 0.50 3 5X 0 . 40 0 . 1 1X 0.5 0.1
1.60
(4X)
0.15 6
TOP VIEW BOTTOM VIEW
4 0.10 M C A B 4 0.25 +0.05 / -0.07
( 6X 0 . 25 )
SEE DETAIL "X" ( 1X 0 .70 ) 0 . 55 MAX
0.10 C
C
BASE PLANE (1.4 )
SEATING PLANE 0.08 C
SIDE VIEW
0 . 2 REF
C
( 5X 0 . 60 )
0 . 00 MIN. 0 . 05 MAX. ( 4X 0 . 5 )
TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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FN6867.1 June 12, 2009

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